Study And Design Of IX Bus In Network Processor

Nowadays, Network Processor (NP) has been paid more attention than ever before, and it is considered as a key technology that will promote the development of next generation communication network. The appearance of NP is thought to be a revolution of the communication industry, so the market has accepted NP's contribution to the communication network development. Many companies and universities also focus on the study of NP.The work in this dissertation is a part of national project entitled" Research and Design of High-performance Network Processors ". Based on the study of IXP1200 Network Processor, its internal peculiar bus module——IX Bus is analyzed in this paper. Through the research on the characteristics of its system and transmission, we know how IXP1200 communicates with each other through IX bus; then we extract schematic from the layout, and validate the circuit; at last, we give the analysis of on-chip-bus by compared with other buses.With the fast development of semiconductor technology, on-chip bus shows some shortcomings. In this paper, based on national 863 project——multi-core processors sharing memory interconnect technology, we thoroughly analyze a new on-chip interconnection architecture——Network on Chip.Through the understanding of on-chip communications, we firstly analyze its characteristics. Then, NoC routing schemes are focused on. After that, an Ant colony algorithm for NoC routing is brought forward, and the parameters in the algorithm are discussed. Finally, this algorithm is verified by several experiments, which prove that it is useful for the NoC communications.