Design And Implementation Of Bus Protocol Of Multi-core Network-processor

With the continuous development of integrated circuit manufacturing process, the chip can integrate more and more functionality. The development of IC products has been experienced the process of the traditional system on board to system on chip (SoC System-on-a-Chip). On-chip bus (OCB:On Chip Bus) technology has become a key technology for SoC designs.On the other hand, with the increasement of system integration level, a notable trend of developing SoC design is multi-core processing. These high-performance multi-core processing SoC system OCB’s a very high bandwidth requirements. How to build a multi-core SoC platform bus interconnect structure effectively has become an important research topic.In this paper, we analyzed SoC architecture and designed the multi-core network processor (XDNP)’s on-chip interconnect bus protocol aiming at the high throughput real-time processing requirements of network processors. By adopting the principle of splitting transmission we divided the Bus into two levels:the control plane and data plane; The control plane bus uses AMBA2.0-AHB bus protocol, the data plane bus employ a dedicated bus protocol structure in which commands and data are separated. Against the Determined plan we designed the detailed timing of multi-processor master bus interface, slave bus interface from the device and the bus arbiter. We complete the protocol hardware design in Modelsim hardware design environment.Finally, we did bus functional simulation for the system. After the bus functional simulation verification we use Synopsys Company’s tool "Design Compile" to compile the command bus arbiter module, the results show that our design can meet the design specifications of index requirements.