Study On Novel TFTs By Simulation

With the continuous development of polysilicon thin film transistors (P-Si TFTs), their applications have been greatly extended. P-Si TFTs have been gradually regarded as ideal alternatives for traditional amorphous silicon TFTs (a-Si TFTs). Compared to a-Si TFTs, P-Si TFTs show obvious advantages such as high carrier mobility, high speed and integration degree, p- and n-type conducting modes, self-aligned structure, low power consumption and high resolution, making it possible to provide brighter and finer display quality. In order to improve the performance of P-Si TFTs, various device structures have been proposed, including the Offset structure, LDD structure, P-N-P gate structure, bi-active-layer structure, double-gate structure, and ultra-thin active layer structure. These structures are effective on optimizing certain properties and suppressing some negative effects of TFTs, and hence helping to promote the extention of their application ranges.The fabrication process of P-Si TFT is quite different than that of MOSFET. Certain key preparation techniques of P-Si TFT were thus introduced by focusing on these differences. Emission microscopy (EMMI), scanning electron microscopy (SEM) and reactive ion etch (RIE) techniques, routinely used in semiconductor research and manufacturing companies, were applied to perform the reliability and failure analysis for the gate oxide layer, which often casues the electrical failure of semiconductor devices.Similar to other semiconductor devices, continuous reduction in the device size of P-Si TFTs may induce many negative effects, for example, the drain induced barrier lowering (DIBL) effect, the hot carrier effect (HCE), and the impacting ionization of carriers near the drain. These phenomena become quite remarkable even when the channel length approaches to around 2μm. In this work, we proposed a novel P-Si TFT structure, namely, Halo LDD structure, which could effectively suppress the short channel effects in P-Si TFTs. The electrical model of Halo LDD P-Si TFT was firstly studied. The threshold voltage and I-V characteristics of the novel structure were investigated by using the process simulation software, Tsuprem4, and the device simulation software, Medici. Comparing the results systematically to those of conventional structure, LDD, and Halo P-Si TFTs, we found that the Halo LDD P-Si TFT showed promising advantages in suppressing the threshold votage drop and shift, lowering the leakage current and decreasing the hot carrier effects. Moreover, the effects of processing conditions of the Halo LDD structure, for example, the implantation dose and the length of LDD structure, the implantation energy, angle and dose of Halo structure, on the threshold voltage, the on- and off-state current, as well as the on/off current ratio, were obtained by detailed simulation. These results can directly provide useful reference for device parameter optimization. Finally, an introduction of the applications and prospects of P-Si TFTs in the liquid crystal display field was briefly presented.