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Design Of RF SOI-LDMOS Device

Posted on:2010-01-31Degree:MasterType:Thesis
Country:ChinaCandidate:J G LiFull Text:PDF
GTID:2178360272482590Subject:Materials Physics and Chemistry
Abstract/Summary:PDF Full Text Request
The RF power device is considered as a very important basis for wireless communication technology. RF power LDMOS is widely used in narrow-band and high-gain technology for wireless communication and is regarded as a very successful RF power device. The advantages are as follows. First, its high constant transconductance in a wide current range creates a large dynamic range of linear amplification, leading to great linear gain when output power is high. Second, the cross modulation distortion level is low. Third, the performance-cost ratio is high. However, the parasitic output capacitance of LDMOS will directly affect its output characteristics, including power gain, power-added efficiency, and so on,especially, can make the design of output matching harder. Compared with LDMOS, the SOI-LDMOS has many advantages that completely dielectric isolation, low output capacitance, high power plus and high temperature resistant characteristic. Its technology which is easier than LDMOS is compatible with SOI CMOS.In this paper, we simulated and optimized the estimated parameters of the device from the mathematical modeling by two-dimensional device simulation software ISE. By optimizing, we have got the optimal parameters of structure. We established the structure model of the device, and simulated the electrical properties of the device with the software ISE. Simultaneously, we discussed the relations of the electrical properties to the structural parameters. By simulating, we found that the device has good characteristics of DC output, lower parasitic capacitance, and higher cut-off frequency. Finally, the failure mechanism of SOI devices and methods of suppression were discussed in details.In order to improve the application of the device in high-voltage and high frequency fields, scholars have put forward various structures. A novel double buried layer partial SOI LDMOS structure is studied. We focus on the breakdown voltage and the output capacitance of the structure. Through the simulation, we found that the device of DBPSOI-LDMOS structure has higher breakdown voltage, and a better frequency feature compared with the traditional SOI LDMOS structure.
Keywords/Search Tags:SOI-LDMOS, parameters, breakdown voltage, electrical properties
PDF Full Text Request
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