Font Size: a A A

Design And Implementation Of Reconfigurable Chaotic Encryption System Based On FPGA

Posted on:2009-12-04Degree:MasterType:Thesis
Country:ChinaCandidate:S ZhangFull Text:PDF
GTID:2178360272470507Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Today, with the development of information technology, information processing scale is far beyond what people have expected. The amount of information raises geometrically, at the same time, the need of protecting important data also increases. These make inevitable challenges to the real world of information processing ability. The traditional single-processor, not-evolution of information encryption mode would no longer meet the current needs of massive data, but the parallel and reconfigurable information encryption mode could provide a solution to these problems.According to the requirement of Chang Jiang RiverWay Department of manage, in this thesis, the reconfigurable encryption system completes real-time image encryption work, before the images are sent to sand mining monitoring system. The system, combining with FPGA-based reconfigurable technology, chaotic encryption technology and the Map/Reduce technology that is used in large-scale cluster system, designs and implements a reconfigurable chaotic encryption system, the system is good to meet not only the current user needs, but also the future evolution of encryption methods, which paves the way for future similar projects and provides an excellent platform for the development.First, this thesis analyzes the user's actual needs and the latest developments of the chaotic encryption technology and parallel computing technology, so a FPGA-based reconfigurable encryption system is designed out. Second, according to the proposal, the thesis carries out overall structural design and various sub-module implement, after the completion of the selection of hardware platform, this thesis achieves the function of the hardware platform and takes advantage of VHDL language to realize the basic logic control algorithm. Then plant the embedded operation system ucLinux and program user controller. Finally, rigorous testing of the system has been carried out to make sure that the system is correct and evolvable. After finishing the system, this thesis makes a summary of the work and proposes the future work prospects.
Keywords/Search Tags:Reconfigurable, FPGA, Chaotic Encryption, Map/Reduce, Parallel Computing
PDF Full Text Request
Related items