Design And Implement Of Image Process System Based On FPGA

With the development of the industry techniques, AOI is flourished and progressing quickly. Facing the challenge, which from the new part specification, another AOI system architecture is brought forward, that is Array, arranged Image System. Recently, the goal is to complete a child system of entire function, and suit for this architecture, including image input, storage, transmission, process, and output module.The image input and process module is the main subject of the paper.The image input module is developed based on the datasheet of the CMOS sensor, which is the main chip for image input module. The job is mainly done on the driver of the chip, and what should be done for the transformation from the raw data obtained from the chip to image data. The design is aimed at the most and accurate original image data of system's highest ability.The design of image process module is mainly discussed on: the structure of the module is based on the data flow, includes data access and data process; and a new and specialized image recognizing method, the principle and implement, veryfication of which is discussed.The system is mainly in the charge of Spartan 3E 1200E, which is produced by Xilinx, corporation, using VHDL language describing the driver and control of the entire system. The development of the CMOS sensor (including timing synchronization, RGB raw data process), 32M SDRAM chip (the inner coding system and DMA control design), gigabit Ethernet communication system set-up (chip IP1000A and implement of UDP protocol based on FPGA), and image process techniques is involved.Experiment proved that, all the function is done in the rough, and the new image process technology is testified. It is reasonable and practical to design ideas and methods showed in this thesis. And these are valuable for developing similar systems.