Description And Synthesis Methods Of Reversible Logic Circuits Based On The Hardware Description Language

Along with the increasing scale and integration of integrated circuits, theirs power consumption has become a large problem, which has now become a bottleneck that restricting the further development of the integrated circuit. Power consumption of integrated circuits are mainly from process irreversible,and the key to reducing energy consumption is not reversible operation becomes reversible operation. The power consumption of integrated circuits are mainly from irreversible process, and the key to reducing energy consumption is making unreversible operation becoming reversible operation. Reversible logic circuit only containing the new circuit of reversible operation which can eliminate energy consumption and heating from information loss. reversible logic synthesis using reversible logic elements implement reversible logical network structure and makes the price as low as possible, it is the basic and key to study and realization of ultra- low power integrated circuits and quantum computers.According to bottleneck in the design of large-scale reversible logic circuits encountering in reversible logic synthesis, the thesis reference successful experiences and achievements of regular(non-reversible) logic design, finding the appropriate method to use hardware description language and EDA tools for describing reversible logic circuit and functional simulation. Combined with the necessary human intervention and correction simultaneously, the thesis achieve(semi) automatic design of large-scale complex reversible logic circuits.The arithmetic logic unit is viewed as a design object, because it is not only typical of large-scale complex common functional unit circuits which can test and improve the method of reversible logic synthesi circuits,but also the essential core component of a quantum computer in the future.Specifically, this thesis presents the basic method of reversible logic circuits based on Verilog description: the 16 bits reversible ALU is designed based on a reversible full adder containing both arithmetic and logic function Which is characterized by multi-operand thus becoming more stronger;the thesis use Verilog describing reversible ALU,at the same time, implement logic synthesis and simulation by Quarter II. In addition, the thesis also presents a mixed description manner designing the reversible full adder for reducing manual intervention further. Preliminary experiments showed that description and synthesis methods of reversible logic circuits based on the hardware description language proposed in this thesis have certain feasibility and effectiveness which maybe have certain reference value and significance for the study of more complex and larger reversible logic synthesis.