Design Of LNA And Mixer In Receiver Front-end

With the development of the wireless communication system towards miniaturization, integration and portable direction, the low cost, high performance radio frequency integrated circuits are paid attention to. The wireless radio frequency circuits are applied in the small equipment and the portable electronic products. The wireless connection and the exchange of information between equipments are realized with RF circuit. The designed low noise amplifier and mixer are the main circuit in front-end of RF receiver in the thesis.The designed circuit mainly includes low-noise amplifier circuit, AGC circuit and mixer circuit in the FM receiver front-end. Low noise amplifier is first level of active circuits in the RF receiver system. LNA circuits have the important impact on the performance of system. Differential input structure is applied in the LNA design. The LNA circuits are composed of controllable gain amplifier circuit and gain control circuit. The gain of controllable gain amplifier is controlled with adjusting controlled voltage. The low-noise circuit is in detail investigated, and the noise source and suppression noise method are in-depth analyzed. Low noise amplifier provides 25dB gain, less than 1dB noise parameter and 2μV sensitivity. AGC circuits are composed of the controllable circuit and controlled circuit. The amplifier gain is adjusted with changing the parameters of AGC. The dynamic range of AGC is 40dB. Based on analog multiplier structure, the addition and subtraction local oscillator signal frequency and the RF signal frequency can be realized with the mixer. The middle frequency signal is the down conversion frequency difference signal. The interference signal and noise are filtered with the middle frequency filter. The operating frequency of mixer is 76MHz to 108MHz, 1dB compression point is 100mV, conversion frequency gain is 15dB, and the noise parameter is less than 1dB. The operating voltage is 2.5 V to 5 V, and the average operating current is 3.6mA.The circuit and layout are designed based on JAZZ 0.35μm BICMOS process. The circuits are simulated and analyzed with Hspice. The layout design of whole circuit is accomplished with CALIBER, and the DRC and LVS are carried out. Presently, the chip has been manufactured, and the circuit is being tested.