Design Of Key Modules In RF Frequency Synthesizer For Wireless Sensor Networks

With the continuous development of wireless communication technology, wireless sensor network (WSN) will mature, and its great value in the field of information perceptionechnology sector bring it a lot of attention. The development of wireless sensor networks requires radio frequency transceiver chipsperform better. This thesis focuses on fractional phase-locked loop (PLL) frequency divider in WSN frequency synthesizers.This thesis designs divide-by-2, divide-by-3, programmable divider, ∑-A modulator and automatic frequency calibration circuitry. All the circuits are based on TSMC 0.18 μm CMOS process and low supply voltage of IV. The divide-by-2 adopts parallel current switch source coupled logic structure. The divide-by-3 adopts the structure of double edge triggerconnected as a loop to guarantee the output pulse rate is 50%. Programmable frequency divider consistes of dual-modeprescale and PS counter. Dual-mode prescale adopts the traditional structure cascaded by synchronous dual mode frequency divider and asynchronous divider to realize the balance of working rate and power. PS counter is designedby the full custom method that can improve the working frequency to use prescale whose frequency dividing ratio is smaller and the programmable divider whose continuous frequency dividing ratio is smaller. E-A modulator adopts improved MASH 1-1-1 structure, which composed of three order error feedback modulator (EFM) cascaded conected and between two adjacent EFM there is a feedforward connection, tominimize decimal strayfinally. Automatic frequency calibration uses frequency detection scheme to strike a balance between work time and circuit complexity and comply with the requirement of the system. The post-simulation results are as follows:the frequency range of the divide-by-2 is 4-8GHz; the frequency range of the divide-by-3 is 0.5～4.5GHz, and the pulse rate is 50%; the frequency range of the programmable frequency divider is 1.0-6.5GHz and the core power is 3.99mW when the frequency of input signal is 6.5GHz; the frequency range of fractional frequency divider is 1.0～6.5GHz, the dividing ratio range is 186.72～221.76 and the core power is less than 4.8mW. Fianl test results of he programmable frequency divider is:chip area is about 0.675mm X 0.378mm, the frequency range is 0.5～6.0GHz and the core power is 3.48mW when the frequency of input signal is 6.0GHz. The test results meet the design requirements.In this thesis, the various modules designed meet the requirements of the WSN system, and have the characteristics of low power consumption. So they can be applied to the WSN core chip.