Rs And Convolutional Concatenated Codec Fpga Implementation

Transmited in the communication channel which affected by various noise, information could be error in digital communication systems. There is another way that the technique of error-correcting codes can improve the reliability of communication system besides expanding bandwidth, increasing transmitted power and reducing systems 'noise.The concatenated codes which made up of convolutional codes which makes full use of correlation of each block and RS codes which is a kind of BCH codes, with the high performance of correcting random errors and burst errors, has been widdly used in communication systems, such as satellite communication, digital video broadcasting(DVB), and mobile communication.According to the project, the concatenated codes system, made up of RS encoding and decoding, convolutional encoding, Viterbi decoding, scrambling, descrambling and frame synchronization, has been designed.Firstly, after discussing the convolutional codes's representation, characteristics and Viterbi algorithm, Bit Error Rate of the systems affected by constraint length of convolutional codes and traceback length of Viterbi algorithm has been Simulated and analysed and given the optimal value for them. To implement Add-Compare-Select Unit (ACSU) and the survivor memory management, trace back(TB) method has been studied in this thesis.Secondly, after discussing the encoding and decoding of RS codes, the concatenated codes's performance has been simulated and analysed under the Gauss channel. In this thesis, BM algorithm has been used to Search the error location polynomial which is the kernel technique in decoding of RS decode algorithm.on ther hand,Chien search circuit and Forney algorithm has been used to search roots of error location polynomial and error value.Thirdly, according to the feature of frame structure and Viterbi algorithm, the frame synchronizer, based on the technique of windowing technique, has been proposal.Lastly, concatenated codes has been realized on FPGA, testing for burst error and random error of information on single circuit board has been simulated and analysed, and the performance of system's encoder has been simulated and analysed too.