Design And Research Of DRAM Controller Of AVS Video And Audio Decoder

As the updated version of the SDRAM, DDR SDRAM(Double Data Rate Synchronous Dynamic Ram) shows its excellent performance in high-bandwidth solutions. In application where high speed and huge capacity memory is needed, DDR SDRAM is broadly used. In memory store subsystem of video decoding system, DDR SDRAM featuring high performance and low price is inevitably the best choice. In this thesis, a DDR SDRAM Controller is designed for video decoding chip.Video and audio decoder has a relatively high demand on the data throughput, so general DDR SDRAM controller can't satisfy the need for real time decoding. Improving the efficiency of the controller is a big challenge to the design. By analyzing the data access request, a reasonable arbitration scheme is determined. Storage method of video data dramatically affects the efficiency of the controller. So in the design. A detailed research is made on arrangement of the video data and a reasonable storage methodology is developed.A Top-Down design scheme is adopted in the design. The design specification, compartmentalization and design of sub-modules, functional simulation and logic synthesis are described in detail in this thesis. Multiple clock domain is one character of this design. Transfer of access information from system clock domain to DDR SDRAM clock domain adopts asynchronous scheme. Rigorous timing requirement is one challenge to the design. Registers which are used to generate the control signals are all needed to be hand-placed to guarantee the phase relationship specified by the DDR SDRAM datasheet.This design is one important part of the 863 project"digital video and audio encoding and decoding chip". The author is responsible for design and validation and sythesisi and formality of DRAM controller. P&R are implemented by back-end team with the instruction of the designer. Design tools of SYNOPSYS Co. are used. This design has been verified by top level simulation of the decoding system and FPGA validation. Simulation result indicates that this controller can supply a bandwidth of 1.1GB/s and the efficiency is 52.3% which can meet the bandwidth requirement for HD real time decoding.