The Design And Research Of MCU Core Based On EM78

With the rapid development of the Electronic Technology, SOC has become the trend and mainstream of IC design. The methodology based on the IP reuse technology, which can improve the design efficiency at a large degree and decrease the cost, is gradually becoming the chief methodology of SOC design. However, 8-bit microprocessor has become a member of IP library and its embedded framework is an important technology and method of SOC design. This paper deals with the design of a MCU core which was compatible with the instruction system of EMC Corporation's single chip. This would build up a solid base for developing special purpose ASICs and realizing IC system integrations in the future.Firstly, the thesis built up an IP model described by Verilog in the CPU of EM78. The IP core model designed in this paper is featured by a Harvard architecture and pipeline operation. It adopts RISC whose instruction length was 13 bits. Consequently, all instructions (57) are executed in a single-cycle except for a few ones and it uses two-level pipeline structure. The IP core is made up of eight modules, which are alu module, pc-point module, clk-gen module, decode module, get-data module, write-back module, RAM and ROM. These modules are described by Verilog HDL and simulated respectively. At last, the top module is simulated and testified correct.However, this system was simplified during the up to down design, and it has obvious differences to the actual circuit. In order to catch up the foreign advanced technology, we should study their successful design experience. Otherwise, we could not get our product's performance and acreage optimized. So it is determined that we adopt the design method combined reverse analysis and top-down design. Then EM78 microprocessor has been studied by investigating the layout, which has been redrew as schematic in blocks. After that, this schematic has been downloaded to FPGA to prove its validity.