Research And Implementation Of Multi-core RTOS Optimization For RISC-V SMP Processor

Instruction set is an interface specification between computer software and hardware.The current mainstream instruction set architectures with the largest market share,x86 and ARM,are not open source,and the use of their architectures needs to face strict patent licensing issues.Our country has been constrained for a long time in terms of chip instruction set architecture,especially in the embedded field,where the ARM architecture has almost formed a monopoly.Realizing independent and controllable core information technology and products is an important strategy in our country’s information technology.RISC-V is an emerging open-source instruction set architecture in recent years.Researching the open-source RISC-V architecture is a possible direction for our country to break the blockade of chip technology.At the same time,the improvement of single-core performance of embedded processors has almost reached the bottleneck,and multi-core parallelism has become the main trend.Multi-core operating systems are very important for embedded multi-core processors.Real-time operating system(RTOS)has always been a research hotspot in the embedded field,and more and more embedded application scenarios have high reliability and strong real-time requirements[1].For RISC-V,the multi-core development boards that can be used for research are relatively scarce at present,so there is not much research on the corresponding RTOS of RISC-V multi-core processors.Researching RISC-V multi-core RTOS and optimizing its shortcomings are of great significance to the development of RISC-V software ecology.This thesis uses the domestic open-source operating system RTThread as the basic platform to study the RTOS of the RISC-V architecture SMP processor,and optimizes the current shortcomings of the RISC-V multi-core RTOS kernel.The core work of this thesis is to optimize the spin lock mechanism and multi-core task scheduling in RISC-V multi-core RTOS.In terms of spin locks,a spin lock mechanism based on RISC-V LR/SC instructions is proposed.In the task scheduling part,this thesis proposes a task scheduling trigger mechanism based on RISC-V software interrupt,optimizes the task scheduling strategy,and proposes a load balancing scheduling strategy based on the CPU candidate pool.Based on the existing implementation of RISC-V multicore RTOS,combined with the characteristics of RISC-V hardware,this thesis analyzes the shortcomings of RISC-V multi-core RTOS,and improves and optimizes it.This thesis uses the classic Dhrystone[2]test program for testing the performance of embedded processors to test and verify it on the K210 and PolarFire development boards of the RISC-V architecture.The test results show that the functions of the optimized RTOS are running normally,and the above improvements can effectively reduce the system time consumption and task scheduling delay,and improve the real-time performance of the RTOS.