Research On And Improvement To Executable Tests Generation From TTCN-3

Network traffic pattern has been constantly changing with proliferation of network application and new network services. Routers and switches, as core devices in subnetworks, have profound impact on network performance. Consequently, performance testing or evaluation of routers/switches becomes more and more important and demands new testing capability in coping with multi-port traffic concurrency. The background of this dissertation is the research work on multi-port concurrent testing method and testing system development of Sichuan Network Communication Technology Key Laboratory (SC-Netcom Lab).SC-Netcom Lab has introduced a generic test method called Multi-Port Concurrent Transverse Test Method (MPC-TTM), which enables testing a single router/switch in all possible operation environments, or evaluating network performance through selected routers distributed in a subnetwork. The Distributed Multi-port Concurrent Test System (DMC-TS) under development at SC-Netcom Lab is an implementation of MPC-TTM, which consists of a Multi-Port Concurrent Test Controller (MP-CTC) and multiple two-port testers (TPT) interconnected to MP-CTC. A TPT controls and monitors the behavior of a pair of ports of a router by executing of tests compiled from abstract tests defined in TTCN-3, either independently or under control of the MP-CTC.This dissertation addresses to issues related to inadequacy and improvement of TTCN-3, in the background of concurrent multi-port performance testing. As a result of this study, a prototype of version 2 of TTCN-3/C++ complier is produced, which provides better support to TTCN-3 functionality and introduces a few new features essential to multi-port concurrent testing. The novelty of this work is to introduce a generic synchronization point insertion mechanism, which not only supports new expanded TTCN-3 but is also applicable to standard TTCN-3. This enables re-utilizing existing test cases in existing TTCN-C, where no explicit synchronization has been defined, in a distributed testing system for multi-port concurrent performance testing for routers. The other extension to TTCN-3 discussed in this thesis, concerns traffic pattern generation,timer,test verdict etc, which create conditions for multi-port concurrent performance testing to simulate real operation environment.Majority development effort described in the dissertation has been directed to fundamental changes to TTCN-3 compiler. V.1. These changes include optimization data structure of compiler, perfect the match of the template,log statement,adapter etc. Uniform adaptation mechanism has been defined in dealing with the adaptation problems. The function of V.1 TTCN-3 compiler has been extended for performance testing.The main contribution of this dissertation can be summarized as: having optimize the data structure and the generating method of TTCN-3 compiler V.1; having introduce synchrony point to approve the distribute test system, and give it's realization;having introduce the structure of the system adaptation and platform adaptation; having introduce the performance test; having carried out preliminary tests on an UDP implementation and RIP implementation in a level-3 switch and shown that the design goal for TTCN-3 compiler V.2 is reached.