Low-Voltage And Low-Power Rail-To-Rail CMOS Operational Amplifier

In recent years, more and more electron with battery supply are widely used,which cries for adopting low voltage analog circuits to reduce power consumption, low-voltage,low-power analog circuit design techniques are becoming research hotspot. In the analog IC (integrated circuit), the operational amplifier took in the most basic unit; its importance is well known. In low voltage operational amplifier, because supply voltage reducing, the signal dynamirange reduces, at the same time, the noise signal scope increases relatively, the amplifier signal to noise ratio reduces. In order to expand the signal the dynamirange, the low voltage operational amplifier usually needs the input signal scope and the output signal scope to be able to achieve the entire amplitude.In view of this question, this article discusses as follows: 1) The thesis has done the widespread investigation and study to the domestic and foreign's technologies of analogy low-voltage and low-power,and analyzes the principles of work, merts and shortcomings of these technologies,based on the absorption of these technologies,the work presents a 1.5V low power rail-to-rail CMOS operational amplifier. 2) The paper designes the theoretics and synthesis of basic cells of a fold-cascode operational amplifier, such as differential input pairs, cascode stages, low voltage wide-swing current mirrors, rail-to-rail output stages, and miller compensation capacitors and so on. In addition, the low-voltage folded cascode input stage, low voltage wide-swing current mirrors, and so on , characteristics analyzed in detail, in order to get extremely excellent performances. 3) The other is the design of amplifier with constant-g_m rail-to-rail input stage. When common mode input voltage changes, it provides nearly constant-g_m, independent of input MOS transistor operating region (strong, moderate or weak inversion), and the quiet nods of the circuit for current addition and the output stage keep unchanged. The output stage use the class AB circuit, encreasing the output voltage swing and reached rail-to-rail, improving the power efficiency of the circuit. 4). The circuit design is realized in 0.35μm CMOS technology and HSPICE simulation results indicate that it consumes only 0.141mW ,achieves 100dB do open gain, 500MHz unity-gain frequency and 68 phase margin for a 100 pF load capacitance. All of pre-defined specifications are satisfied with the simulation results.