Characteristics Research Of Ultra-Deep-Submicron SOI SiGe MOSFETs

Si/SiGe technology has been noticed and investigated because of the advantages such as high carrier mobility. However, the strained-material devices reported currently exhibit some defects, which can be summed up as:(1) The manufacture of strained-Si channel NMOS and strained-SiGe channel PMOS need different strained materials, so the manufacturing processes are not compatible, it is very difficult to integrate the strained-channel n- and p- MOSFET on the same substrate.(2) The existence of Si cap upon the channel of PMOS weakens the electrostatic potential control ability of the gate, when the gate bias increases, the hole carriers transfer from SiGe channel to strained-Si channel, this behavior forms a surface parasitic channel, which weakens the performance of PMOS.(3) The strained-channel MOSFETs are still under the single-gate(SG) control mechanism, so they can not solve those problems effectively such as short channel effects(SCEs) when gate length scaling down to ultra deep submicron, and therefore these questions obstruct the development of the critical dimension (CD) to a shorter characteristic dimension degree.As mentioned above, a novel fully-depleted SOI device structure with double-gate and dual-strained-channel is presented in this paper. The novel device structure with gate length scaling down to 25nm is established, the theories about the double-gate devices are summarized, and the models of strained Si and strained SiGe are modified in order to obtain more accuracy simulation results. Both the steady-state characteristics of single device and the transient characteristics of CMOS are analyzed under SG and DG control mechanisms by the adoption of ISE TCAD. The factors such as Ge percent and back gate bias that influence the performance of the novel device are analyzed; the characteristics of PMOS under both SG and DG control mechanisms are simulated and compared at the same time. The three main problems mentioned above can be solved effectively by the adoption of the novel structure according to the simulation results:(1) The strained-Si and strained-SiGe are combined together in the novel structure and consequently the dual-strained-channel is formed. Both the NMOS and PMOS have the same vertical stack and can be achieved by changing the doping species and amounts, so their manufacturing processes are compatible.(2) The novel structure can work under both SG and DG control mechanisms. When the device is used as SG MOSFET, the strained-Si channel and strained-SiGe channel are control by the top and bottom gate separately, the driving currents are improved for both NMOS and PMOS compared with the unstrained ones, the conversion time from Logic 1 to Logic 0 are reduced to about one half compared with unstrained CMOS simultaneously. For PMOS, both the electrostatic potential control ability and the driving current are improved significantly by the adoption of bottom gate control mechanism, the surface parasitic channel is diminished at the same time.(3) When the device is used as DG MOSFET, it shows strong gate control ability, when the gate length scaling down to ultra deep submicron, those problems such as SCEs and so on can be improved significantly, the steady-state and transient characteristics can be improved further compared with SG control mechanism.At the end, the technical feasibility of the novel structure is discussed. Typical strained-material devices and their manufacturing processes are introduced, typical DG device and the manufacturing process is introduced too, the manufacturing process based on the novel structure is presented , we can draw the conclusion that the novel structure can be achieved with today's process level.