Research On The Design And Implementation Technology Of Dual-field Modular Arithmetic Logic Unit

Elliptic curve cryptography is widely used in digital signature,key agreement,identity authentication,information encryption and other security fields.With the development of research,there are many international standards for ECC.Different elliptic curve standards have different signature schemes,key exchange,information encryption and other protocols.The implementation of ECC depends on the basic modular arithmetic of finite field layer such as modular multiplication,modular division and modular addition-subtraction.Therefore,based on the arithmetic of finite field layer in ECC,this paper focuses on the key problems in the design of length-scalable dualfield modular architecture logic unit.In the research of hardware implementation of elliptic curve cryptosystem,there are two kinds of realization of finite field layer modular architecture logic unit.One is the addition circuit structure,the other is the multiplication circuit structure.The hardware circuit based on adder consumes less resources,but the operation speed is not fast enough.With the increase of processing bit width,the critical path delay of adder increases,which slows down the overall performance.The hardware circuit design based on multiplier structure has the characteristics of high speed,but the hardware resource consumption is large.Based on the design of small bit width multiplier and adder,it is not conducive to the realization of modulus division algorithm.The implementation of a round of addition takes many clocks,and the time of modulo division is very long.while the design of large bit width multiplier is suitable for modular operation with fixed bit width,which is not flexible and general enough.The structure of systolic array is simple and regular.Its critical path delay is small and does not increase with the increase of processing bit width.Systolic array structure is suitable for the addition operation in the modular arithmetic.Therefore,this paper designs the the addition modular architecture logic unit based on the systolic array structure.In order to shorten the critical path of the circuit and improve the frequency of modular architecture logic unit,the Radix-2 Montgomery modular multiplication algorithm and Greatest Common Divider(GCD)modular division algorithm are improved in this paper.In Montgomery modular multiplication algorithm and GCD modular division algorithm,the next round of operation is determined by the lowest bit of the result of this round.Only using systolic array structure,after one round of operation,two clocks are required to start the next round of operation,and the operation clock cycle is doubled.In order to reduce the clock cycle,this paper uses the circuit structure of 4-2 compression circuit and systolic array adder to design a dual-field length-scalable systolic array architecture logic unit,which can realize the modular multiplication,modular division,modular addition-subtraction of any length within 576 bits.The circuit maximum clock frequency is 1.43 GHz,which can meet the implementation requirements of elliptic curve cryptosystem with different security levels.In order to meet the requirement of high speed,this paper presents a scalable dual-field multiplier modular architecture logic unit,which can consider the performance of modular multiplication and modular division.This paper improves the original Montgomery modular multiplication algorithm.By calling KO algorithm and KO-3 algorithm,the clock cycle of modular multiplication operation is effectively reduced.The circuit structure combining the multiplier and the adder can realize the modular operation in parallel and improve the operation speed.A highspeed dual-field multiplier modular arithmetic unit is designed,which can perform modular arithmetic with variable length in prime field and binary field.The experimental results show that the modular architecture logic unit can realize the dual-field modular operation of of any length within 573 bits.It only needs 63.8ns to realize 573 bits modular multiplication,and 1.66 us to modular division.