The Key Technology Of The Communication Architecture Of Two-dimensional Mesh NoC

Integrating multiple processors on the single chip to improve the system performance has been becoming a trend. And how to heighten the communication efficiency of processors is the key issue of the multiprocessor system design. The traditional design of the system chip was based on the bus infrastructure. Although, it is easier to be designed and implemented, but the IPs (Intellectual Property) that connect to bus need to share the bus bandwidth, So this is a restrict to improve the communication efficiency. While, the communication method of network-On-Chip (NoC) is like to the network communication. It has the better communication efficiency. In this paper, based on two-dimensional mesh NoC, we establish the communication protocol, design and implement the whole communication infrastructure. And then, we validate the entire design, and testify that the network communication infrastructure has better efficiency than bus.This dissertation is supported by the following projects: the project of 'Basic Research of Networks-on-Chip Architecture and the design Methodology' supported by the National Natural Science Foundation of China (NSFC,№:60576034); the project of 'Research of On-Chip-Network Key Technology of Networks-On-Chip' supported by the Specialized Research Fund for the Doctoral Program of Higher Education (SRFDP,№:20050359003).The main work and achievement are as follows:1. Designed the NoC system model based on two-dimensional mesh topology, and put the research emphases on the design of communication model.2. Proposed the communication protocol, which is simple, but can meet the research need. Based on this protocol and two-dimensional mesh topology, we designed the NoC system architecture.3. Designed and implemented the Resource-Network Interface (RNI) and proposed the software model, which cooperate RNI to complete the transmission and receival of the data package.4. Validated the entire design by dynamic-track-display experiment. We make use of Stratix II EP2S180 FPGA of ALTERA to prototype the whole system, which includes hardware and software. The experimental results showed that this NoC system prototype can steadily run at 38.25MHz.5. Designed the pipelined-matrix-multiplication experiment to validate that, the network communication infrastructure of two-dimensional mesh NoC has better performance than the bus communication architecture.