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Research Of Processing System For IF Digital Receiver Based On FPGA

Posted on:2009-08-28Degree:MasterType:Thesis
Country:ChinaCandidate:S Z XuFull Text:PDF
GTID:2178360245950738Subject:Agricultural Electrification and Automation
Abstract/Summary:PDF Full Text Request
Software Define Radio (SDR) is now a hot subject to be researched in the filed of radio. But ,due to the limitation of hardware development level , the digital structure of medium frequency of board brand with the sampling function are widely used, which has become the critical technology for the realization of this structure. Traditionally, FPGA devices were used to achieve the purpose of processing mostly base on the complex programming of VHDL and the main obstacles of high difficulty and long cycle time are not avoidable. This paper first introduced the definition of SDR, and then performed research on digital medium frequency of board brand base on Matlab/DSP Builder for the realization of FPGA, meantime it completed the simulation both under the environment of matlab and Quartus platform.The main task and conclusion summary:(1)in order to improve the complexity of FPGA programming method of medium frequency of board brand in traditional means. It suggested a design plan of window interface which is based on Simulink/SDP Builder. The plan takes advantages of SignalCompiler modul to convey the Simulink model file into VHDL code which in required by the realization of FPGA. By this way, the terseness and efficiency of the realization of FPGA which is based on the VHDL programming digital electrical system can be achieved as well as the simplification of the complexity of the design.(2)To provide carrier waves needed by signal demodulation. it designed NCO, which is base on the direct digital frequency synthesize (DDS).according to the certain interval of phase , it stored the binary data of the wave range to be generated into high speed memory as the lookup table. use the reference frequency source as a clock .let the frequency control word to decide the phase interval of wave data to be drawn from the lookup table, by which different out put frequency can be generated. The experiment result shows that, The NCO can provide the frequency reference source with high stability and precision.(3)To slow down the signal speed and extract useful signal . it suggested to use the method of Multi-level cascade to achieve the function of lowpass. Designed CIC filter,HB filter and FIR filter three classes of filter. It was used under the lower frequency and the parameters were optimized . much easier to realize and more hardware sources were saved. (4)In order to provide the actuator for system simulation. Designed the AM modulator base on the amplitude signal as one example and use it as the input signal to perform the simulation on the designed system. The experiment result suggests that this module can meet the design requirements very well.
Keywords/Search Tags:SDR, digital IF, FPGA, simulation
PDF Full Text Request
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