The Design And Simulation Research Of∑-△Analog To Digital Converter In FPGA

The structure of oversampling analog to digital converters(ADC) based on sigma-delta(∑-△) modulator was first put forward in1963for video signal transmission.∑-△ADC consists of a∑-△modulator and a digital downsampling filter, it has the characteristics of high resolution, low power consumption and low cost. Compared with the traditional Nyquist rate ADC,∑-A△ADC which adopts the techniques of oversampling, noise-shaping and digital-filtering, has lowed the requirements for analog circuit imperfection and component matching, and can overcome the limitations on resolution that can not be achieved by the traditional Nyquist rate ADC. Additionally, the field programmable gate array(FPGA) and digital signal processing(DSP) techniques make the∑-△ADC more easier for the integration on one chip with other digital circuits. Currently, along with the rapid development of the very large scale integration(VLSI) circuit and system on chip(SOC), the∑-△ADC has become a feasible solution for a high precision ADC design.As the core of∑-△ADC, the performance of∑-△modulator directly affects its resolution. Thus, the research and design of∑-△modulator seems to be important. By analysing the principle of∑-△ADC and the structure of first-order and second-order∑-△modulator, this dissertation puts forward a high precision ADC solution with a field programmable gate array(FPGA) chip. The method uses the low voltage differential voltage signal interface(LVDS) within FPGA. along with a minimum number of external RC components and an oversampling digital filter, a two-order∑-△ADC can be implemented inside the FPGA devices. By building an ideal model of a two-order∑-△ADC in Matlab and Simulink, and doing the behavioral simulation, we can conclude that the output signal has an signal-to-noise distortion ratio(SNDR) of-86.7dB and an effective number of bits(ENOB) of14bits. which meets the performance of the ADC. it is also successfully verified by the EDA simulation tools.The method proves that it not only has advantages of simple implementation, convenience and flexibility, but also high integration.This dissertation firstly uses the top-down method and simulation tools, such as Matlab and Simulink to design the arithmetic of the analog to digital converter module, and then according to the arithmetic module, the Synphony Model Complier AE(Synphony HLS) can automatically generate the Verilog HDL source code and its testbench. Finally, we use the integrated design tool Libero to verify this code and testbench to complete the design of∑-△ADC based on FPGA. The method is not only more convenient and simple, but also has high integration and low area. It is easier to immigrate and can foresee the circuit performance and give a correct guidance on designing circuits to the IC circuit designers. It is widely used in high resolution, high speed, low voltage and low power loss fields such as digital audio processing, measurement of the instrument, medical electronics and wireless communications. Hence, the system design has good practical and broad market prospects.