Hardware Design And Improvement Of Synchronization Core Node In OBS Network

The hardware design of the core code in OBS network is studied in this paper. The paper begins with the description of architecture of the OBS test bed, which is composed of three edge nodes and four core nodes. The design of main control unit of the core is described in detail. Four optical modules are used for the O/E translation of serial signal. Two chips named S2064 are responsible for the reception and transmission respectively and one side for serial signal is connected to the optical modules, the other side for parallel signal is connected to the FPGA. The Synchronization of the reception is accomplished by S2064 itself and that of the transmission is achieved by making the associated clock on line output by the S2064 for receiving to be the reference clock of the S2064 for transmitting, which insures the synchronization not only between core node and external data line but also among different core nodes. The transmission speed of the network reaches about 17Mb/s. The whole system is tested after the design. The problems in this design are also discussed and many approaches for optimizing circuit and system are put forward.A detailed design and analysis of OXC is presented in this paper, including the design of matrix driven modules and high-voltage power supply. On the basis of circuit simulation and test, the power supply is composed of a transformer at 50hz and filter network formed by capacitors and the matrix driven module is made up of capacitor charging circuit and power MOSFETs, which outputs adjustable high level pulses with voltage level from 400V to 500V and frequency from 100hz to 1Mhz.