The Research And Design On High Speed CAN-bus Transceivers Based On CMOS Process

CAN bus is a popular field bus, and it is one of the serial communication networks, which supports the distributed controlling and real time controlling system. Now its application spreads rapidly from the automobile industry initially to automation, aerospace, marine, machinery industry, robotics, CNC machine tools, medical equipment, sensors and other fields. CAN bus ICs have formed a huge market. It is monopolized by foreign multinational semiconductor companies.There are very few domestic papers published on CAN bus chip design. Thus, it is very significant for us to develop our own CAN bus transceiver with independent intellectual property. In this paper, a high-speed CAN transceiver fully compatible with the ISO11898 standard based on standard N-well CMOS process is achieved.According to the ISO11898 standard and CAN2.0 protocol, the block diagram of the CAN transceiver is shaped firstly. It includes Driver Control Circuit, Output Circuit, Slope Control Circuit, Bandgap Reference, Thermal Protection Circuit and Receiver Circuit. Each module and the whole circuit are simulated by Hspice using CSMC 0.5μm N-well CMOS process. The results show that, the operating parameters of the chip are fully compatible with the ISO11898 standard. Its performance and functionality reach the intended objectives, and some modules even exceed the original parameters.Compared to most of the CAN transceiver chips fabricated by bipolar or BiCMOS process in the market, the transceiver in this paper is designed based on standard N-well CMOS process is not only an innovation, but also a useful experiment. Low cost CMOS process is the main trend in low voltage-low power consumption design.In the transmitter part, a chain of cascaded inverters is used to drive two large size complementary MOSFETs. The total propagation delay of the driving circuit is approximately 5 ns, and the biggest drive current is 420 mA. Coupled with two gate resistors, the output waveform on the bus is symmetrical without spikes. In dominant state, the differential voltage on the bus is 2.6V (CANH=3.75V, CANL=1.15V).In recessive state, the differential voltage on the bus is 0V (CANH=CANL=2.5V). This not only meets the requirements of a high-speed operation, but also ensures sufficient drive capacity to the bus.The slope control circuit is realized by four variable micro current sources, which can control the gate capacitances of the output MOSFETs to charge or discharge.The slew rate of output signal could be adjusted by external pin, so it is very convenient to be used in different transfer rate and mode. Chip manufacturer just need to make very simple changes to introduce several models of different chips according to the market demands.This paper introduces a voltage bandgap reference circuit which uses a self-bias cascoded current mirror. This structure uses tow resistors to replace bias circuit. The output voltage range is wider. With a very small temperature coefficient and an excellent ability of power rejection, it could provide a stable DC bias for the transceiver and ensure an accurate shutdown threshold point for the thermal protection circuit. Double BE junctions are used to enhance the thermal sensitivity of the thermal protection circuit. The thermal oscillation is solved effectively by a positive feedback. In the receiver part,a 0.4V hysteresis voltage comparator eliminates the differential mode noise interference effectively. When in the dominant state (CANH-CANL> 0.9V), the receiver shifts to a low logic voltage. When in a recessive state (CANH-CANL <0.5V), the receiver shifts to a high logic voltage.Several harsh operating conditions are also took into account, such as over-voltage protection, short circuit protection, thermal protection and the thermal stability of the receiver circuit. The output waveform of the transmitter has very high symmetry, which reduces greatly its external electromagnetic radiation and brings the chip high stability and reliability.