Study Of Implementing Wavelet Transform And Reconstruction With Hardware

Wavelet transform is a very important production in the phylogeny of mathematics. It has strongly impacted on both mathematics and engineering applications. The discrete wavelet transform (DWT) has been used as the core transforming technology in JPEG2000, a newest static image compression standard.Firstly, this thesis analyzes the theory fundamental of wavelet transform in details, and also introduces mufti-resolution analysis (MRA), Mallat algorithm and Lifting Scheme. Comparing with the traditional DWT, the Lifting-based DWT is lower implementation complexity and less hardware resources. After analyzing the specifications of Very Large Scale Integration circuit (VLSI) design, we obtain the design idea and methods of 2D DWT chip based on Lifting Scheme. Especially in the transform module, we use the shift-add technique, the pipeline technique, and the two-way RAM technique to optimize the architecture. The optimized architecture results in the merits: regular input/output data stream, strong independence and flexibility, low hardware cost, simple architecture, intrinsic parallelism, high percentage of hardware utilizing.Using the above methods, the hardware architecture of Le Gall 5/3 wavelet filter is obtained in this thesis. Then we implement 2D DWT in the register transfer level (RTL) using the hardware description language Verilog HDL. We also successfully simulate the architecture in RTL. The result of simulation is the same as that of Matlab simulation, which proves that the designed architecture is correct and practicable.