ASIC Design And Implementation Of Packet Buffer Management Unit

With the fast development of high-speed network, the processing data amount of network equipment increases accordingly. The traditional packet buffer management mechanisms are unable to meet the requirement of large-amount packet buffering due to low memory utilization rate. This article puts forward a high-performance implementation of packet buffer management that has the advantage of high memory utilization rate as well as low cost, high access bandwidth and reusage.The beginning of the article introduces the function of packet buffer management and two kinds of traditional packet buffer management mechanisms. Then the random-access packet buffer management technique is introduced and its advantages are illustrated. In our solution, packets are chopped into 128byte cells. The goal of random access to memory as well as the high utilization rate of memory is achieved through using the high-speed SSRAM to maintain the cell linktable. And the requirements of high bandwidth and low cost are also met through using FCRAM to store packet data. A series of solutions that aim to increase the access bandwidth of memory and ensure the compatibility of different kinds of SSRAMs are also put forward according to the practical applications. Finally, the simulation and testing schemes to packet buffer management unit are roughly introduced based on the implementation.This design has been implemented in a million-gate scale ASIC chip that is embedded in a PoS Monitor (Packet over Sonet Monitor) system, providing the packet buffer management function to dual path of 5Gbps data rate in SONET.