The Design And Implementation Of Data Queue Management In Broadband IP Network

With the development of flow classification design in network monitor, traffic billing or QoS offering system, data queueing management for classified packets gets more and more complex. Also in the rapid growing broadband IP network, such as SONET, the data queueing management is widely used on dealing with huge traffic streams and different service classes in a wire speed. At the beginning, this thesis introduces several data queueing management technologies based on software and hardware implementations. Then it gives an ASIC solution of high-speed data queueing manager design based on hardware technology. In this solution, we used configurable buffer management and centralized queue management methodologies which provide compatibility to various RAM products and multi-queue management. Also the RAM accessing bandwidth and multi-queue operation efficiency are optimized in this design. At last, this thesis presents the simulation and verification plan to the solution. This design has been implemnted on a milion-gate scale ASIC chip, which has been integrated on a SONET packet-processing system, and provided data queueing management to 5Gbps traffic over 2 OC48 channels.