Research And Design Of Nested Miller Compensation Amplifier

The rapidly increasing integration densities of integrated circuit technologies has forced some fundamental changes of direction in the field of analog integrated electronics. Demands on accuracy and noise, the design emphasis has shifted from the basic qualities towards the ability of circuits to operate at a low supply voltage, consuming a minimum amount of power. Associated with the transition to low voltage circuit design is a demand for frequency compensation techniques that are dedicated to the new context: compensation strategies which decrease the power consumption, but above all which are capable of handling the specific demands of the low voltage amplifier topologies. Moreover, it is of great importance to study the amplifier as a general block in analog circuit. Supported by National Science Foundation of China and Sichuan Province Academic and Technologic Leaders Foundation, we have held deep research in low voltage amplifier and the compensation technology.oIn this paper, an amplifier based on nested miller compensation technology applied to a low dropout linear voltage regulator has been designed. At first, we introduce the general part of the amplifier given necessary basic theory for the work. Then we explain the whole process of design to the need of special characteristic.Considering the parameter of the operational amplifier, we design the two-stage amplifier based on nested miller compensation. Then we analysis the cascode structure, common resource output stage, frequency compensation technology and power supply rejection ratio of the amplifier.After that, on the basis of the UMC 0.5um 2P2M CMOS model, HSPICE simulation results which includes the gain, differential mode input range, common mode input range, power Supply Rejection Ration, common mode rejection ratio and slew rate. With the normal loads, an open-loop gain(Av) of 87dB, a unity gain bandwidth(GB) of 1.2MHz, a phase margin( Φ) of 63°, and a power supply rejection ratio(PSRR) 75.6dB have been achieved for a VDD of 3V.