Research On Routability-driven Placemment Algorithm For Hierarchical Field Programable Gate Array

Under the Very Deep Sub-Micron technology, placement becomes the key part of VLSI design.In addition, thanks to the predictability of the routing resources, placement plays an imperative role in FPGA design.Aiming at the higher perfermonce and lower congestion, this thesis mainly focuses on the FPGA architecture model and related placement algorithm. The thesis proposes a versatile hierarchical FPGA(HFPGA) architecture model and gives the corresponding mathematical model. It implements the high accuracy routability-driven placement algorithm for HFPGA based on interconnect wire model and the fast diagonal placement algorithm using the diagonal hierarchical level instead of the wirelenth.The algorithm's effectiveness is evaluated by the experimental results of MCNC benchmark. Finally, it establishes the interface for the routing and can finish global routing founded on its data structure. The proposed FPGA architecture model and the related algorithm provide the use for reference for industry.