| In the modern electrical system, FIR digital filter is widely favorable for many applications due to its well linear phase characteristics. With very fast development of modern electrical technology, FIR filters with high- speed and low-power are required in engineering. So there is a recent boom in designing high speed and low power FIR filters in this field. Up to now, it is universally acknowledged that the main processing frequency of FIR filters depends on the operating period of multipliers , and then the multiplication algorithm may affect the performance of multipliers. Thus, by improving the multiplication algorithm, one can speed up the operations of FIR filters; even can reconfigure the architecture for the implementation of FIR filters, considering system delay. In the sequel, exploring effective multiplication algorithms and constructing suitable architecture of FIR filters are of considerable significance, which are also the focuses of this thesis. The main works are introduced as follows.At first, we propose an algorithm to decompose the fixed point signed multiplicator into two sub-components with minimal nonzero digitals, which reduces the number of partial products potentially. Moreover, this multiplication algorithm can provide multiple representations and expand applied places, when comparing this algorithm with the traditional CSD representation. Additionally, extensive simulations have been performed and these outcomes are confirmed.At second, a novel algorithm, transforming coefficients of the FIR filter, is developed by selecting the suitable common coefficient and the corresponding weights with a greed approach. In comparison with traditional ones, we find that this algorithm could efficiently improve the processing speed of FIR filters.At last, in order to achieve further high performance of FIR filter, we synchronously apply two algorithms mentioned above to optimize coefficients of the FIR filter and reconfigure its architecture. |
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