Thermal Stress Analysis Of Stacking Chip Scale Package Under Power Load

With the rapid development of information technology, the microelectronics devices are widely used. The temperature fluctuations on chip will be generated by turning on or shutting off the power source, which cause the appearance of thermal stress among materials. At present, the packaging industry has done plenty of works to the reliability in thermal load while the study of power load is very less. Compared with the thermal load, power load can simulate the mechanics of actual heating of chip. So the research of die thermal stress under power load has an important theoretical significance and practical application foreground.In this paper the finite element analysis software ANSYS has been used to simulate the thermal stress distribution in stacking chip scale package (SCSP) under power load. The results show that the maximum Von Mises stress on die is 143 MPa under power load, which is close to the die crack strength, and it is the main factor for the die destroying. The maximum shear stress on the die is 65.4 MPa. The shear stress on die is apt to cause the split between the die and the package material. During the die working, the temperature is 412.09K and the high temperature influences the die speed and reliability.The influence of the material's thickness and thermal expansion coefficient on the die reliability is simulated. The results show that the temperature on silicon die decreases and the reliability of the device increases with the increase of the silicon die volume, and the die stress increases with the increase of thermal expansion coefficient of the molding compound and the epoxy paste.Through the research of the package material and structure, the package model is optimized. The highest temperature, maximum stress and shear stress are 408.48 K, 95.2MPa, 35.4MPa respectively after optimizing. The optimized design can decrease the temperature of the die and device and improve the function and reliability of the die.The dies are analyzed by power load under different process. The results show that the device integration level and the temperature of the die increases with the improvement of process level. When the processing level reaches 0.13μm, the increase of the die heat generating rate will cause the accumulation of the heat, which affects the die function and reliability seriously. When the processing level reaches 0.15μm, the stress is large enough to destroy the silicon, then the package material and the system structure need to redesign.The thermal distribution of the 0.25μm processing die is simulated. Compared with the power load analysis, the load condition of thermal analysis is temperature. It is convenient to use thermal analysis when the load temperature is the same and the load condition is power, which is accurate to use the power load analysis when the analysis condition is thermal source.The research result provides theory to support the further optimizing for the material parameter and improve the device function. It has an important significance in SCSP design.