Thermal modeling and stress analysis of packaged semiconductor devices

To tackle the ever increasing power density and complexity of integrated circuits and Printed Circuit Boards (PCB), a systematic approach to thermal modeling at chip and board levels is developed using analytical and numerical methods, respectively. The near real-time chip level analysis utilizes the analytical temperature solution of an infinite multi-layer plate structure with an embedded circular source, the circular unit thermal profile method, method of images and Kirchhoff's transformation. With the complex and irregular geometry of the PCB, the finite element (FE) method is used for its capability and flexibility in modeling complex geometry and mixed boundary conditions. The resulting temperature profile from this complete chip and board thermal model has a refined chip level temperature distribution and an accurate temperature contour for both package and board. This complete modeling approach is applied to analyze GaAs RF power devices in a plastic Small Outline Integrated Circuit (SOIC) package mounted on a PCB. The SOIC package is simulated at the PCB level to understand the thermal paths and percentage of power removed from the die by each path. The FE results show that only 5.7% of the heat escapes through the molding compound and copper lead surfaces by free air convection. The remaining 94.3% conducts through the leads to the board, indicating the great importance of the thermal design for the board. Experimental thermal measurements using liquid crystal microthermography are performed to validate the modeling results. Because a leadframe serves as the essential heat carrier in a package, thermal characterizations of two leadframe designs are studied. Effects of leadframe material, die-attach, and molding compound are explored. Also, thermal enhancements such as thermal slug and thermal via in plastic packages and PCBs are investigated quantitatively. Besides thermal failures, stress related failures on chip-bonded devices due to thermal expansion mismatch are gaining importance as the electronic industry continually tries to pack larger die into a thinner package. The FE technique is utilized to model the nonlinear die-attach material properties under thermal stress loading. Three bonding materials are studied with silicon and GaAs chips to understand how the stresses are developed.