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Thermal management of chip scale atomic clocks

Posted on:2008-05-31Degree:Ph.DType:Dissertation
University:University of Colorado at BoulderCandidate:Laws, Alexander DavidFull Text:PDF
GTID:1448390005970020Subject:Engineering
Abstract/Summary:
Power dissipation for chip scale atomic clocks is one of the major design considerations. The largest power usage, 20 mW, is for temperature control of the vertical-cavity surface-emitting laser (VCSEL) and the alkali-metal vapor cell, each must be maintained at 70+0.1°C even over large ambient temperature variations of 0°C to 50°C. Two design approaches for solving this problem are analyzed herein.; The first approach is to utilize heat produced by the clock's control electronics, 10 mW, to help heat the cell and VCSEL in order to reduce overall power to below 30 mW. This is achieved by integrating the cell and VCSEL with the electronics, and packaging the entire module in a well insulated electronics package. However, if the package is very well insulated it will overheat when the ambient temperature is high because of heat produced by the electronics. A bimetallic snap disk based thermal switch and a variable thermal resistance (VTR) package have been developed to release the additional waste heat and keep the clock from overheating. The bimetallic snap disk based thermal switch can change a test clock package resistance from 0.31°C/mW to 0.14°C/mW and has been well characterized by experiment and FEA modeling. The design of the VTR package has been evaluated using FEA modeling and has been shown to reduce power below 30 mW and flatten the power versus temperature curve.; The second approach is to treat the cell and VCSEL as a discrete electronic component to be integrated with the other clock electronics. This approach relies on a small amount of power, 12 mW, to maintain the physics package temperature by suspending it on a specially designed Cirlex structure and vacuum packaging it in a low emissivity coated enclosure. The thermal performance of the physics package has been evaluated by FEA modeling and experimentation and was found to have a thermal resistance of 6.28°C/mW. The structural performance of the physics package has also been evaluated using FEA and experimentation and will survive an 1800 g shock of any duration in any direction without exceeding the Cirlex yield stress, 49 MPa.
Keywords/Search Tags:Clock, Thermal, FEA modeling, Cell and VCSEL, Power, Package
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