Design Of A CPU Core Compatible With MCS-96

Embedded MCU is playing a more and more important role with the technology development, and the search in MCU has always been a focus of electronic engineers. To satisfy the industry requirement and improve the performance of MCU, a CPU core which is compatible with the MCS-96 MCU, is designed in this paper. MCS-96 family is CHMOS MCU of Intel, and its instructions are easily to be used and are flexible in programming. The CPU core in this paper is able to operate on 54 instructions of the instruction set, which means 111 opcodes, and space is prepared for further development.The CPU core is deviede into Data-path and Contrel Logic, and pipeline is used during the operations. It is composed of the RegFile, the Register Arithmetic Logic Unit (RALU), the Control Unit and the Interruption Controller.The RegFile is an array of SRAM synthesized by the Memory Compiler.Most of the data processing is done by the RALU. The design of RALU is based on the resource sharing strategy, and the logic operation unit is predigested, aiming to reduce the operation types.Control Unit controls the rhythm of CPU. In the design of the Control Unit, Instruction Length Counter and Instruction Step Counter are brought in to produce control signals.Interruption Controller is able to deal with interruptions of 16 different levels, generate the Interruption Request Signal and corresponding vectors.Results of simulation show that the design is able to implement all the given instructions correctly. Synthesis is done when the frequency is 40MHz and no timing violation is made. Simulation result after synthesis is also right.