Design Of Adaptive-Bandwidth BICMOS PLL For VHF Wireless Receiver

With the development of integrate circuit and communication technology, low power and single chip FM(Frequency Modulation)receiver, which works at VHF band (76MHz-108MHz), is widely used in the field of FM stereo broadcast, domestic security and defensive systems, entrance guard systems. PLL(phase locked loop) as the core of the receiver which has the great influence on SNR of FM receiver, so the research on the PLL circuit has the great significance on it.The purpose of this thesis is to research the PLL frequency synthesizer suitable for FM receiver. Based on the specification of synthesizers, advance Adaptive-Bandwidth PLL design which have settled the contradiction between acquisition time and phase noise. The PFD is designed for no dead zone and the outputs of PFD adopt complementary output. The charge pump circuit adopts fully difference structure which can inhabit common mode disturber perfectly and the area is decreased by substituting active load for resistors. The structure of programmable divider adopts dual-modulus presale architecture of 2/3 which enables easy layout work and decrease the design time. The circuit design based on the Current Routing Logic (CRL) principle which is suitable for optimization of each cell by down scaling the tail current. VCO(Voltage Control Osscillator) adopt active negative resistor oscillator which introduce high Q external inductance and varicap minished the chip area and the phase noise of VCO. In the simulation of whole PLL circuit, VCO and programmable divider model is established in Verilog-A language which have decreased simulation time and also make the close loop simulation become possible. In the whole circuit simulation, the stereo signal is established in Verilog-A language which bring the simulation more truthfulness.Finally, the result of chip simulation indicates that the total power consumption of PLL circuits is 12mW with 3V supply voltage, Acquisition time t settle≤1ms, channel switch time t switch< 1.4ms, phase noise -123dBC@1MHz. The whole PLL circuits meet the specifications of FM receiver.