Design And Verification Of Data Cache Bank

Cache has becoming an absolutely neccessary function component in the high performance microprocessor. Its speed, reliability and power has been the main criterions to evaluate the performance of microprocessors. In fact, the level of Cache technology would have been an important measure of improving performance of microprocessor.On the basis of deep research on Cache technology, in this paper, there is a design of a internal Data Cache with its size of 16Kbytes in X-microprocessor and it is organized as a 4-way set associative Cache. There are 128 sets in each Cache.The main contents of this paper are as follows:Firstly, order to improve Caches work speed, in the design of Data Cache Bank there are some typical designs: one is to let Caches and TLB work in parallel mode, the other is to optimize functional component through adding buffer unit in data access.Secondly, there are the designs of Date Cache: encoder circuit, parity circuit, Sram unit and sense amplifier, and so on. Simultaneously, the X-microprocessor employs a pseudo-LRU replacement algorithm and adopts MESI protocol.Finally, we progress logic stimulation and Ultrasim simulation aiming at our design, and gain good verification in System Level.The stimulation results show that the design could function corretly with good performance. The designs have been applicated in X-microprocessor, which has been tapped out successly now. The results of the chip testing show that the design could accord entirely with the X-microprocessor's needs.