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The High Performance Operational Amplifier Research And Design Based On Power Management Chip

Posted on:2008-09-12Degree:MasterType:Thesis
Country:ChinaCandidate:P LiFull Text:PDF
GTID:2178360215965005Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Accompany with the development and maturity of CMOS technology, the performance of CMOS device has a large improvement in speed, power consumption and frequency response, these modifications provide the possibility of design and manufacture the CMOS OP Amp with high performance. Especially for the portable electronic products in low power consumption applications are more likely to design with this technology. Designing a high performance CMOS amplifier with high output current which used in power management chip is the main target of this paper.Because of the widely use of portable electronic products with battery-powered, so the requirement for power management chip is critical, which must has a small size, low power consumption, and high power convert efficiency, meanwhile some also has a high performance and high output current OP Amp inside. This kind of power management chip is usually used for active matrix, thin-film transistor (TFT), liquid crystal displays (LCD), etc. The built-in OP Amp can drive the LCD backplane (VCOM) directly, which provide the convenient power management resolutions for engineers.To realize the above goals, a CMOS OP Amp is designed in this paper, which has high output current, constant DC gain, wide power supply range. The input stage of this OP Amp use constant gm and complementary input construction, which can deal with the rail to rail input signals. The output stage use miller compensation and feed-forward class AB control output manner, this architecture guarantee the output stage has a high power efficiency and rail to rail output voltage range. The layout of OP Amp is designed by the UMC 0.6um DPDM BCD technology. HSPICE simulate result indicate that the OP Amp can work well with the supply range from 4.5V to 8V, other parameters are: 121dB open loop gain, 18MHz bandwidth, 13.7V/us slew rate at rising edge and 14.2V/us slew rate at trailing edge, 90dB power rejection ratio typically, 60°phase margin. These performance parameters are sufficient for the requirements of the power management chip. This OP Amp has a more important use value.
Keywords/Search Tags:Analog Integrated Circuit, CMOS, Amplifier, Rail-To-Rail
PDF Full Text Request
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