Studies On LDPC Codes And Its Hardware Implementation

Low-Density Parity-Check Code is a kind of channel code with near Shannon performance, which can achieve outstanding performance even under the extremely low signal to noise ratio, and hence is now a research hotspot in the coding field. This paper performs deep studies on the theory and hardware implementation of LDPC codes respectively, and finally completes the hardware design of its encoder and decoder structure.With regard to the theory research, the structure of LDPC codes and several methods of parity-check matrix construction, i.e. the Gallager Code, semi-random LDPC,quasi-cyclic LDPC (QC-LDPC), and irregular LDPC, are studied. Then, the traditional encoding algorithms and effective coding based on approximate lower triangle matrix are analyzed in detail. Finally, the sum-product (SP) decoding algorithm and log-SP decoding algorithm are highlighted, and the quantization problem of decoding is studied deeply. An effective decoding quantization scheme for LDPC decoding is proposed, which is able to greatly reduce the hardware implementation complexity while remains good performance near to the floating decoding.With regard to the hardware implementation, firstly, the parity-check matrix and generate matrix of LDPC code are constructed by using the Matlab programming. Then, computer simulation is performed on its encoding and decoding, and the proposed decoding quantization scheme is verified. Finally, hardware design of the inner parallel encoding and log domain SP decoder are accomplished on the ISE software platform by the Verilog HDL language.