Research On Encoding And Decoding Algorithm Of IRA-LDPC Used In DVB-S2 Standard

Compared with the DVB-S standard, the DVB-S2 standard (The Second Generation Of Digital Video Broadcasting For Satellite Application) has greatly improved, the modulation is promoted to 16APSK, 32APSK from 8PSK, performance is greatly improved by adaptive coded modulation and the Error-correcting capability achieves about 3dB improvement. The reason why DVB-S2 has a better performance is due to the LDPC code which is a new achievement of the development of channel coding.The LDPC code is a series of linear block code which can be defined by sparse check matrix or Tanner graphs. The LDPC code has a powerful error-correcting ability and the decoding performance can be close to the Shannon Limit. However, its encoding is complex. The LDPC code applied to the DVB-S2 standard constructed by an irregular cycle cumulative way, with a cycle-encoding feature, can partly solve the problem of high complexity of encoding. Soft-decision decoding algorithms are commonly used to decode LDPC codes. Although the performance of decoder has been greatly improved by Soft-decision decoding, but the decoding complexity, the number of iterations and the latency of the decoder is still need to be addressed. According to the comparison of different algorithms, we find that the SPA algorithm has the best performance with the largest complexity, the MinSum algorithm has the worst performance but with the least complexity, the modified MinSum algorithm can split the difference of SPA algorithm and MinSum algorithm, it can adapt practice better.Firstly, this dissertation illustrates the construction of the IRA-LDPC in DVB-S2 standard particularly and implements the encoder using C platform. Then this dissertation further researches the decoding algorithm principle of IRA-LDPC, devises the floating-point algorithm used in the DVB-S2 standard and achieves the performance of various decoding algorithms. Based on the traditional mechanism of message passing between check nodes and variable nodes, this dissertation presents a new mechanism of serial message passing. Simulation results indicates that not only does the improved the schedule reduce the number of iteration to 30 times from 50 times, but gains about 0.1 dB decoding performance as well under the current decoding complexity. The last but not least, the IRA-LDPC decoder is carried out fixed-point algorithm design. Adapting fine-tune the accuracy of the information at the entrance of the LDPC decoder, compared to precision adjustment adapting bit as a unit, this method addresses the LDPC decoder to the entrance of the information sensitive issue better.