The Design And Achievement Of The Inverse Multiplexing MPEG2 Transmission With Four E1 Interface

With the exigent demand of speed and bandwidth of telecom data, the network built past is the one based on voice transmission, which can not suitable for the current demand. However, to build a new width network need many invest and the building period is long, and it can not meet the recent need for high speed data transmission of the special custom.Inverse multiplexing separates a signal high speed data flow at the sending terminal and transmits it into two or more low speed data links, then reverts them at receive terminal. A design which inverse multiplexing transmission CMOS chip with multi-path E1 based on FPGA is proposed in this paper, which adopt four El to construct clarity transmission panel of high speed data and it supports max corresponding delay time 64ms among E1. Through the adjusting mechanism of link capacity, some link of E1 can be added or deleted dynamically, realizing flexible and high efficient utilizing the high data transmission of real time video, data on network, it can save bandwidth resource and meet the custom's need.The system has sending part and receiving part. The sending circuit realizes frame operation with four El, data splitting adopts a method combining circuitry circulation OR operation and insertion among frames, when A path is inserted a frame (30s interval), then B path is insert data, with the same way, all data are inserted calculatedly among the four E1. The receiving circuit decodes with HDB3 firstly, synchronal orientation of frame secondly, judges circuitry delay thirdly, and then multi-data could be kept consistency by FIFO and SDRAM, at last according to the promissory frame format of high speed data flow the data are output. The whole digital circuit adopts VHDL hardware describing language to design, the simulation are tested.