Design Of High-speed Data-receiving Card Based On CPCI Bus

Data transmission and storage is the groundwork of digitalsignal process and has important effect on the digital system performance.With the development of information technology, the data amount is rapidlyincreasing, which raises higher demand for the high-speed large-volumedata recorder performance.In the context of SAR-data acquisition and storage application, thisthesis studies the design and implementation of a high-speeddata-receiving card based on CompactPCI bus. This design, originated fromthe receiver unit of data recorder in CASSAR-EL01 project, adopts 64bit66MHz cPCI system bus to meet the demand for high-speed-data transmission.On this card, SN65 series high-speed receivers convert the differentialsource signals to single-end ones; two IDT72T36135M chips build up the4MB-volume FIFO buffer by depth-expansion; MAXII series CPLD implementsthe logic connect between FIFO buffer and the card local bus; PLX PCI 9656functions as a bridge between cPCI and local bus.The thesis firstly narrates the whole frame of the receiving card andthe configuration of each functional module chip, and then relates apreliminary analysis on the signal timing and integrity issues, lastly,includes the WinDriver-architecture debugger program in Windows OS.