Design And Implementation Of Ethernet Over E1 Interface Chip Based On FPGA

The paper is derived from the project of Xi'an supermicro electronics Co. LTD., Which discussed system design and realization of Ethernet interface chip.This paper expounded the configuration and work principle of digital integrated Ethernet interface chip EOE1 systematically. During the process, we took into account synchronous clock and amending the design index and functional requirement according to market demand. The thesis made detailed investigation in synchronous circuit design, gave brief presentation to Ethernet and El, and then introduced the function and performance of the chip. The paper designed the performance testing scheme in detail, analyzed the testing result, as well as improved scheme which validated the performance of the chip better. The whole design was described with Verilog language, which also simulated by NC-Verilog of Cadence. Nowadays, the Ethernet interface chip EOE1 has been validated by FPGA.