Prototype Design Of Algorithms, Used In A VFC Chip And RTL Implementation Its Scaling Module

With the development of science and technology, a diversity of display devices are put into market including PHP, LCD, CRT, RPTV and etc. For most types of monitors, their input video formats and required internal formats have different parameters which include scan rate, scan standard, resolution, etc. Due to the versatility of real-world video formats, format conversion has become an indispensable part in modern video display systems. And video format conversion technology has been the focus of research for a long time. Many ICs have been produced by American and Taiwan companies, while R&D in this field is just initialized in our country.As an important part of the Video Format Conversion Chip project brought forward by Tianjin Science and Technology Committee, this thesis is to discuss video algorithms, C prototypes and RTL coding of the scaling module. This whole project focuses on developing a new multi-functional video/image standard conversion ASIC which can realize de-interlacing, frame-rate up-conversion and scaling. Developing our own video/image conversion SOC has great meanings in breaking the market monopolization of foreign companies and speeding the progress of our TV and related industries.This thesis proposes a new motion adaptive de-interlacing algorithm which integrates edge-preserving median filtering algorithm and average filtering algorithm together by weight. This new algorithm has the advantages of easy-implementation and high-hardware-utilization. This thesis also describes the design scheme of a scaling block in detail, which is built on multilevel scaling strategy and row-based pipeline structure used in a video format conversion SOC.Up to now, we have finished three important parts of project, they are: high- performance video processing algorithms, C prototyping of those algorithms and RTL implementation of the scaling module.