The Research Of Video Coding Algorithm And The Realization Of Video Communication System Based On DM642

Coming with the information time, the technologies of information processing, especially the video information processing, have been developed rapidly. The video communication system has been widely applied in video telephone, video conference, video monitoring and other fields. As a result of the large number of digital video information, Video Coding algorithm is becoming the key of the video communication system. Video Coding algorithm needs to process lager number of video data. Digital Signal Processors have a good performance in handing data. The realization of Video Coding algorithm based on DSP(digital signal processors) has drawn great attention.The recommendation H.263 which can be used for compressing the moving picture component of audio-visual services at low bit rates was proclaimed by ITU-T (International Telecommunication Union) in 1998. The recommendation H.263 can be used in video telephone, video conference, video monitoring and other fields. It not only use inframe transform coding technique,but also use interframe predictive coding technique. Its compressibility is much higher than JPEG. It's emphasized that the recommendation H.263 serves low bit rates and supports the video coding standard to the video services at low bit rates . The basic configuration of the video source coding algorithm is based on Recommendation H.261 and is a hybrid of inter-picture prediction to utilize temporal redundancy and transform coding of the remaining signal to reduce spatial redundancy. H.263 uses interframe prediction to eliminate temporal redundancy, DCT transromation to eliminate spatial redundancy and variable-length code to eliminate symbol redundancy. The source coder can operate on five standardised picture formats: Sub-QCIF, QCIF, CIF, 4CIF and 16CIF.The DM642EVM, which is based on the second-generation efficient and advanced VelociTI very long instruction word architecture, is developed by Texas Instruments, and using such DSPs is an excellent choice for digital media applications. The DSP core of the DM642 is 32-bit fixed-point DSPs of C64x, with the performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600MHz. The DM642 uses a two-level cache-based architecture, Level 1 cache is composed of a 16-Kbit L1P (level 1 program cache) and a 16-Kbit L1D (level 1 data cache), Level 2 cache consists of 256-Kbit memory space that is shared between program and data space. The peripheral elements include: three configurable video ports, a 10/100 Mb/s Ethernet MAC (EMAC), a management data input/output (MDIO) module, a VCXO interpolated control port (VIC), one multichannel buffered audio serial port (McASP0), an inter-integrated circuit (I2C) Bus module, two mulitchannal buffered serial ports (McBSPs), three 32-bit general-purpose timers, a user-configurable 16-bit or 32-bit host-port interface (HIP16/HPI32), a peripheral component interconnect (PCI), and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.Through studying the H.263 Video Coding Algorithm in this paper, the H.263 Video Coding/Decoding Algorithm have been transplanted successfully in the DM642. In the paper it is said in detail how to transplant the algorithms. The algorithm is optimized in memory managing and function level, and it's run time has fit the request of our project. The H.263 Video Coding Algorithm in the paper has been used in real project and plays a good performance.In the paper a new point to point video communication system has been designed and implemented based on the DM642. In the system, the DM642 gets the analog video data from analog camera. The analog video data turn to digital data through SAA7115. The digital video data is coded in the DM642 with the H.263 Video Coding, and then the coded data is send to the LAN though network port. At the same time the DM642 receives the coded data from other terminal in the LAN. The coded data is decoded in the decode task, then the data becomes digital through SAA7105 or SAA7121.At last the video data is displayed on TV or other display devices.The system is designed on RF5 of TI. RF5 is intended to enable designers to create extensive applications that use numerous algorithms or channels. In contrast to lower Reference Framework levels, RF5 uses blocking threads (tasks). As a result RF5 can be used in applications that have complex interdependencies between threads. RF5 provides a scalable channel manager, TSK-based application, efficient inter-task communication, structures thread-safe control mechanism, easy replacement of I/O drivers, allows easy debugging etc. So this system uses RF5 as the base of the program.The designed and implented details about the end to end video communication system on the DM642 in this thesis are : (1)the video port and relevant drivers design on DM642; (2) the theory study of TI reference framework 5 and the construction of application program on RF5;(3)the study of TI NDK;(4)the communication between tasks;(5)the design of multi-task program .A steady and fluent embedded end to end video communication system based on the DM642 has been implemented by this dissertation. The system can be a self-governed video communication system which can run steadily a long time. It achieves the demands of the design. The system can be used in video telephone, video conference, video monitoring and other fields and has practical meaning in some degree.The implementation of video coding algorithm and video communication system based on the DM642 is a new research field. In the thesis H.263 Video Algorithm has been implemented successfully on the DM642 and designs a point to point video communication system.