Design And Experimental Research On The Low-Spur Radar Signal Simulator

High precision, low spur (low noise) and high real-time property are the basic requirements for radar signal simulator's performance. And the performance required is more and more high with the development of radar technology and the appearance of new system radar. Our main work is to study the crucial technological problem of wideband, low-spur radar signal simulator, including architecture, design and realization, test and experiment and so on.The performance of the radar signal simulator is analyzed in this paper, and kinds of architectures and the plan for implementing the radar signal simulator are discussed in detail. In order to minimize the radar signal simulator's output spurious signal, a distributed multi-DSP parallel architecture to implement the radar signal simulator is adopted, which is composed of a microcomputer and a multi-DSP system. The wideband characteristic of radar signal simulator requires it must have the high data throughput and the high real-time property. Therefore, the universal serial bus (USB) is adopted in this paper to complete high-speed data exchange between microcomputer and the multi-DSP system, which both guarantees the radar signal simulator's real-time property and minimizes the electromagnetic interference between micro- computer and the multi-DSP system.The signal generator system based on digital signal processor TMS320VC33 is designed in this paper, and the signal integrity of the hardware system is analyzed. The data transfer system based on USB 2.0 is an important part of the simulator, which realizes the high-speed data transmission between microcomputer and the multi-DSP system. The USB specification revision 2.0 and the USB peripheral controller CY7C68013 are researched in this paper, and the principle of high-speed data transmission system based on CY7C68013 ispresented, then the hardware system is developed, eventually, the software related to the data transmission of the system is sealed as a ActiveX control in order to be used expediently in the simulator software system. Regard to the logic control circuit of radar signal simulator, a field programmable gate array (FPGA) component is used, which reduces the hardware PCB area and improves the reliability of the hardware system. At last, the functions of the radar signal simulator hardware system are debugged, and the performance of the hardware system is tested in this paper. The results of experiment illustrate that the simulator designed by author fulfils the technology requirements. And this system provides the experimental foundation and the valuable experience for developing higher performance radar signal simulator.