Accurate estimation of design metrics in deep submicron circuits: RLC interconnect delay and crosstalk induced power

The advent of the deep submicron (DSM) era was accompanied by a number of challenging effects that severely impact the performance of modern integrated circuits. In this thesis, we present models and methods for the correct estimation of two design metrics: RLC delay and crosstalk induced dynamic power. We develop an efficient analytical model for the loop self inductance that accurately estimates inductance at a given frequency. This model can be used for fast and accurate RLC delay calculation. The simplicity, precision and efficiency of our model can greatly facilitate any application that requires fast estimation of inductance, such as inductance aware physical synthesis. We also present an integrated methodology for analyzing crosstalk induced power dissipation in cell based digital designs. Techniques for estimating the switching and short circuit power are presented. A new cell pre-characterization technique for estimating the additional short circuit power is developed. A heuristic for computing the additional energy on a switching victim net is also presented in this work. Results demonstrate that the models and techniques developed in this work are accurate and efficient.