Implementation Of H.263 Video Encoder Based On TMS320DM642

The major content of this thesis is the development of H.263 video encoder based on TMS320DM642 platform. The thesis is composed of three parts: the research of H.263 video compression standard, the structure characteristics research of TMS320DM642 and the optimization of H.263 video encoder based on TMS320DM642 platform. In this thesis author finishes work and gets progresses as follows:In this thesis, the video compression standard H.263 is discussed in some detail and some new features of H.263, i.e. selectivity of its model. I do research on ME algorithm completely. As a result, I propose the DS algorithm by analyzing and comparing the FS, TSS and DS algorithm. At the same time, I adopt the optimization of software pipelining and assignment of memory by analyzing DM642's VelociTI structure and Two-Level Internal Memory.H.263 video encoder is successfully migrated from VC++ platform to the TMS320DM642 platform by modifying parameter, header file, function lib and setting CCS compile option, memory space. This moment, the encoder ratio is 0.103f/s. After that, by adjusting encoder flow chart, ratio achieves 0.5f/s. By dividing Cache L2 into 128k Cache L2 and 128K SRAM, ratio equal 3.92f/s and Cache L2 hit equal 96.96%. By placing frequent used data and code segment in memory in chip and others in external memory, ratio increase to 4.67f/s. Finally, optimization of program level is indispensable. The thesis takes advantage of software pipelining, TI image lib and CCS optimal option. These skills enable ratio into 35f/s. That is to say, the encoder is a high compress radio and high quality image real-time encoder.