ESL Design Of The H.264/AVC Encoder

ESL design methodology has become a trend of the chip design nowadays, as the increase of the complexity of the SOC design, the market competition, and the pressure of cost reduction. This new methodology is based on IP modules. And it starts with the system architecture and then the traditional hardware and software design followed. This thesis specifies the architecture of ARM with dual coprocessors implemented on the ESL platform including the design and the performance evaluation. This system is assumed to apply for the H.264/AVC encoder.Based on study of H.264/AVC standard and the complexity analyses of the encoder, this thesis first brings forward the brandnew method for reference frame selection, based on which the new architecture for speeding up the encoder is proposed. With the provement of the feasibility, the standard compliance of parallelization coding and the expansibility of the ARM with coprocessors architecture, this thesis emphasizes on the key design and implementation points of the system on the ESL platform, including the software design and configuration for each core, and hardware design of the interruption controller on the ARM SOC Designer platform. Moreover, with ESL platform, the thesis verifies the control between ARM and coprocessors.