Research And Implementation Of The Data Parallelism Coprocessor Architecture

With the rapid development of the remote sensing technology and the expansion of the mount of the sensing data, the image manipulation nowadays desiderates the super high performance for the data processing to satisfy the real-time requirements. But facing the characteristics of the data-intensive applications, e.g. the image manipulation, the traditional processor architectures are unable to supply enough data processing abilities. Thus, a feasible way is to design a new data parallelism coprocessor, which is good at the data-intensive processing, to solve the real-time problem in the image manipulation.The characteristics in the data sense applications take a great challenge to the coprocessor architecture. Some processors nowadays are lack of the hardware resources, but others are too complex. Thus, they are not competent for the parallelism of the operation. This paper suggests that the chip should not only own abundant resources, but also emphasize a simple and distribute-control architecture, that is to say, the modularization and the distribution of the function units as well as the hierarchy of the architecture become more and more important, and they may gain the simple design of the function units, the locality of the intra-connection and the effectivity of the inter-communication at the same time.Through the analysis of the application background and the contrast to the traditional architecture, this paper proposes its new design idea. On the one hand, the coprocessor adopts a calculation model based on the trigger operation along with its corresponding architecture, to solve the complexity problem cause by an amount of resources. On the other hand, it sets eight clusters, each of which employs lots of arithmetic units and enough effective connections, to achieve the better performance for processing the parallelism data.Firstly, this paper proposes the coprocessor architecture, and designs the instruction format, the cluster structure, the function unit and its memory sub-system. This coprocessor has the characteristics of the hierarchy and the modularization, and supports the scalability and the sub-word.Secondly, this paper designs an automatic generator. This tool can estimate all the architectures for different applications, and choose a suitable one. Then, this tool generates the hardware descriptions of the coprocessor rapidly from the corresponding architecture above.Thirdly, this paper does lots of research on the instruction compressiontechnology. A new compression technology named as PCPP is proposed for the RISC at first. Then, the mechanism of the instruction template is introduced to improve the previous compression techlonogy. As a result, a satisfactory result is achieved and the corresponding decompression prototype is gained.Fourthly, this paper divides the coprocessor into three parts - decoder, function unit and the memory sub-system for running the respective function testing. Besides it, it also proposes some new methods for the chip testability to increase the design efficiency and shorten its test time.Finally, this paper discusses the coprocessor deployment according as the performance testing of the typical algorithm, and compares the performance of the C64X to a signal cluster with the same resources. The experiment results show that the single cluster has a prior to the C64X, which effectively prove its ability of the parallelism data processing.