HMAC/SHA-1 IP Design Based On TPM Specification

This article mainly presents an Hash Message Authentication Code (HMAC/SHA-1) IP core based on the Trusted Platform Module (TPM) architecture with pre-layout synthesis and FPGA verification. We first introduced the TPM hardware structure, several focus points of Trusted Computing and HMAC and SHA-1 algorithms. After that, the design flow of HMAC/SHA-1 IP core is elaborated with detailed functional module division and state machine diagram. To increase the usage rate of HMAC and SHA-1 in TPM, we defined the performance requirements and finally devised the HMAC IP core, which supports automatic message length calculation. To improve the performance of the IP core, 4-2 compressors and Carry Look Ahead Adders (CLAA) are employed. Based on this two technologies and optimization of the SHA-1 architecture, we get pronounced improvement on the calculation capacity. The highest frequency rises from 40MHz up to 100MHz. The following FPGA and functional verification demonstrated the advantage of our IP core. Finally, we propose the summarization of the whole project.