Interleaving And De-interleaving Algorithm Study And Implementation On FPGA

The paper studies algorithm and hardware implementation method of the interleaver and deinterleaver in the DAB (Digital Audio Broadcast) system. There are several hardware implementation methods on time interleaver and deinterleaver, in This thesis choose one practical and optimization method for design tested on FPGA develop board by comparing and analyzing the property of the implementation methods. The key factors on the time interleaving design are interleaving speed, circuit area and memory unit. The paper adopts one port SRAM to implement the design in order to use less memory and the optimization design methods to improve the circuit area. The hardware implementation of the time deinterleaver adopts industry EDA standard Top-to-Down idea, and using verilog Hardware Description Language describes the deinterleaver, and utilizing Cadence Nc-verilog simulator, debugging with Debussy, synthesising with synopsys tool and tests on the FPGA develop board made by Aletra. The result says: The function works well, and better speed and smaller area are used.