Fast Verification Environment Of Image Process Arithmetic

Development cycle of ASIC design is very long. Cost and time are the most important.So we have to verify adequately before type out.The digital image processing verify flat could verify the function fastly and adequately. It replace ASIC with FPGA which has the advantage of fast.The DVF include the following two parts: software and hardware.Software used to verify a series of similar arithmetic and see the validity. FPGA Hardware used to verify the actualize risk of the ASIC. Simulate the real condition of the ASIC working.Evaluate the result in the display system. Hardware includes image capture system, image display system and A/D system.Noise will add to images because of external environment and image system itself, when the image systems are making or transferring images. Denoising is necessary for improving the quality of the images. Median filter is a common denoising algorithm. This paper proposes a new adaptive weighted algorithm based on the slope of the curved liner. Experimental result shows that this algorithm has better characteristicon edge preservation and depression of the noise.We will describe the prosecc include software result compared, hardware ASIC coding and image denoise effect in DVF.